From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate
 requires CS stall
Date: Thu, 25 Oct 2012 11:28:43 -0700
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To: Chris Wilson <chris@chris-wilson.co.uk>
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On Tue, 23 Oct 2012 12:42:07 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > "If ENABLED, PIPE_CONTROL command will flush the in flight data  written
> > out by render engine to Global Observation point on flush done. Also
> > Requires stall bit ([20] of DW1) set."
> 
> That quotation doesn't make sense in the context of TLB invalidation,
> and the programming guide here very carefully avoids the mention of
> requiring any stall bit set for the post-sync op of TLB invalidation.
> 
> Maybe quote chapter and verse as well?

I thought the "Also Requires stall bit ([20] of DW1) set." was pretty
clear?

-- 
Jesse Barnes, Intel Open Source Technology Center