From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 02/10] drm/i915: Add dev to ppgtt Date: Thu, 25 Oct 2012 13:48:42 -0700 Message-ID: <20121025134842.6eae5282@jbarnes-desktop> References: <1350956055-3224-1-git-send-email-ben@bwidawsk.net> <1350956055-3224-3-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id A2DF09EB7C for ; Thu, 25 Oct 2012 13:48:42 -0700 (PDT) In-Reply-To: <1350956055-3224-3-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 22 Oct 2012 18:34:07 -0700 Ben Widawsky wrote: > Some subsequent commits will need to know what generation we're running > on to do different pte encoding for the ppgtt. Since it's not much > hassle or overhead to store it in the ppgtt structure, do that. > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index af0e97e..bf628c4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -344,6 +344,7 @@ struct intel_device_info { > #define I915_PPGTT_PD_ENTRIES 512 > #define I915_PPGTT_PT_ENTRIES 1024 > struct i915_hw_ppgtt { > + struct drm_device *dev; > unsigned num_pd_entries; > struct page **pt_pages; > uint32_t pd_offset; > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 5751ad2..2b75028 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -78,6 +78,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) > if (!ppgtt) > return ret; > > + ppgtt->dev = dev; > ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; > ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, > GFP_KERNEL); > @@ -219,7 +220,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, > switch (cache_level) { > case I915_CACHE_LLC_MLC: > /* Haswell doesn't set L3 this way */ > - if (IS_HASWELL(obj->base.dev)) > + if (IS_HASWELL(ppgtt->dev)) > pte_flags |= GEN6_PTE_CACHE_LLC; > else > pte_flags |= GEN6_PTE_CACHE_LLC_MLC; > @@ -228,7 +229,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, > pte_flags |= GEN6_PTE_CACHE_LLC; > break; > case I915_CACHE_NONE: > - if (IS_HASWELL(obj->base.dev)) > + if (IS_HASWELL(ppgtt->dev)) > pte_flags |= HSW_PTE_UNCACHED; > else > pte_flags |= GEN6_PTE_UNCACHED; Reviewed-by: Jesse Barnes It would be nice if you did some penance for bloating our structures a little though, maybe by removing at least 3 fields from our dev_priv struct? :) -- Jesse Barnes, Intel Open Source Technology Center