From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 06/10] drm/i915: Stop using AGP layer for GEN6+ Date: Thu, 25 Oct 2012 13:55:50 -0700 Message-ID: <20121025135550.4552d75e@jbarnes-desktop> References: <1350956055-3224-1-git-send-email-ben@bwidawsk.net> <1350956055-3224-7-git-send-email-ben@bwidawsk.net> <20121023125724.16b00131@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy11-pub.bluehost.com (oproxy11-pub.bluehost.com [173.254.64.10]) by gabe.freedesktop.org (Postfix) with SMTP id 5B736A0AC1 for ; Thu, 25 Oct 2012 13:55:51 -0700 (PDT) In-Reply-To: <20121023125724.16b00131@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 23 Oct 2012 12:57:24 -0700 Ben Widawsky wrote: > On Tue, 23 Oct 2012 16:58:50 +0200 > Daniel Vetter wrote: > > > On Tue, Oct 23, 2012 at 4:57 PM, Ben Widawsky wrote: > > > Actually, after we introduce the FLSH_CNTL patch from Jesse/me later in the > > > series, I think we just want a POSTING_READ on that register. It is > > > technically "required" by our desire to some day WC the registers, and > > > should synchronize everything else for us. > > > > > > After a quick read of memory_barriers.txt (again), I think mmiowb is > > > actually what we might want in addition to the POSTING_READ I'd add. > > > > Imo we have special rules for the igd, since clearly not all registers > > in our 4mb mmio window are equal. So I'd prefer the keep the readback > > of the last pte write (to ensure those are flushed out) and maybe also > > add a readback of the gfx_flsh_cntl reg (like I've seen in some > > internal vlv tree). Just to be paranoid. > > -Daniel > > What's your definition of flush? I think we just need one read to > satisfy the device I/O flush, and I think the write to the regsiter > should satisy the TLB flush. That leads me to the conclusion that just > the POSTING_READ of the FLSH_CNTL register is sufficient. > > If you want me to do both, I have no problem with that either, and I'll > just update the comment to say that we believe it is unnecessary. > > I don't really care either way. Yeah we just need one or the other, not both. Technically the UC write of the flush control reg should flush the WC buffer, then a posting read of the flush control reg should make sure it gets to device 2 before the read returns. -- Jesse Barnes, Intel Open Source Technology Center