From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/5] drm/i915: implement
 WaDisableRenderCachePipelinedFlush
Date: Mon, 29 Oct 2012 22:33:12 +0100
Message-ID: <20121029213312.GW5691@phenom.ffwll.local>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
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On Thu, Oct 18, 2012 at 12:21:17PM +0100, Chris Wilson wrote:
> On Thu, 18 Oct 2012 11:49:51 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Comment says for eaglelake/cantiga, but it's listed in the ilk table,
> > too. So apply it to both.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Looks harmless due to the massive number of other p/c errata and that
> pipelined render cache flushes have never been relied upon.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

I've queued the first two here for -next (since they don't seem to fix any
reported bugs).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch