From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths Date: Wed, 31 Oct 2012 00:54:35 +0100 Message-ID: <20121030235435.GE5755@phenom.ffwll.local> References: <1351522766-2719-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id DB85AA0921 for ; Tue, 30 Oct 2012 16:53:29 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id n13so338238eaa.36 for ; Tue, 30 Oct 2012 16:53:29 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1351522766-2719-1-git-send-email-mika.kuoppala@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Mika Kuoppala Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 29, 2012 at 04:59:26PM +0200, Mika Kuoppala wrote: > Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical > with regards of workaround introduced by: > > commit 27c1cbd06a7620b354cbb363834f3bb8df4f410d > Author: Chris Wilson > Date: Mon Apr 9 13:59:46 2012 +0100 > > drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g > > Signed-off-by: Mika Kuoppala Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch