From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 02/11] drm/i915: Add SURFLIVE register definitions Date: Wed, 31 Oct 2012 23:57:00 +0100 Message-ID: <20121031225700.GK5755@phenom.ffwll.local> References: <1351698624-26626-1-git-send-email-ville.syrjala@linux.intel.com> <1351698624-26626-3-git-send-email-ville.syrjala@linux.intel.com> <20121031132305.6b3474ed@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id B20599E7BB for ; Wed, 31 Oct 2012 15:55:55 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so1027524eek.36 for ; Wed, 31 Oct 2012 15:55:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20121031132305.6b3474ed@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 31, 2012 at 01:23:05PM -0700, Jesse Barnes wrote: > On Wed, 31 Oct 2012 17:50:15 +0200 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > Signed-off-by: Ville Syrj=E4l=E4 Fails to apply here somehow. Also, this thing is base64 encoded, which confused my normal workflow for a bit ... Dunno what exactly caused this havoc. -Daniel > > --- > > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > > 1 files changed, 7 insertions(+), 0 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index da8400a..2555986 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3041,6 +3041,7 @@ > > #define _DSPASIZE 0x70190 > > #define _DSPASURF 0x7019C /* 965+ only */ > > #define _DSPATILEOFF 0x701A4 /* 965+ only */ > > +#define _DSPASURFLIVE 0x701AC > > = > > #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) > > #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) > > @@ -3050,6 +3051,7 @@ > > #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) > > #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) > > #define DSPLINOFF(plane) DSPADDR(plane) > > +#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) > > = > > /* Display/Sprite base address macros */ > > #define DISP_BASEADDR_MASK (0xfffff000) > > @@ -3095,6 +3097,7 @@ > > #define _DSPBSIZE 0x71190 > > #define _DSPBSURF 0x7119C > > #define _DSPBTILEOFF 0x711A4 > > +#define _DSPBSURFLIVE 0x711AC > > = > > /* Sprite A control */ > > #define _DVSACNTR 0x72180 > > @@ -3160,6 +3163,7 @@ > > #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) > > #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) > > #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) > > +#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) > > = > > #define _SPRA_CTL 0x70280 > > #define SPRITE_ENABLE (1<<31) > > @@ -3194,6 +3198,7 @@ > > #define _SPRA_SURF 0x7029c > > #define _SPRA_KEYMAX 0x702a0 > > #define _SPRA_TILEOFF 0x702a4 > > +#define _SPRA_SURFLIVE 0x702ac > > #define _SPRA_SCALE 0x70304 > > #define SPRITE_SCALE_ENABLE (1<<31) > > #define SPRITE_FILTER_MASK (3<<29) > > @@ -3214,6 +3219,7 @@ > > #define _SPRB_SURF 0x7129c > > #define _SPRB_KEYMAX 0x712a0 > > #define _SPRB_TILEOFF 0x712a4 > > +#define _SPRB_SURFLIVE 0x712ac > > #define _SPRB_SCALE 0x71304 > > #define _SPRB_GAMC 0x71400 > > = > > @@ -3229,6 +3235,7 @@ > > #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) > > #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) > > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) > > +#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > = > > /* VBIOS regs */ > > #define VGACNTRL 0x71400 > = > Reviewed-by: Jesse Barnes > = > -- = > Jesse Barnes, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch