From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 01/11] drm/i915: Fix display pixel format
 handling
Date: Thu, 1 Nov 2012 16:03:13 +0200
Message-ID: <20121101140313.GL3791@intel.com>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
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On Wed, Oct 31, 2012 at 01:20:23PM -0700, Jesse Barnes wrote:
> On Wed, 31 Oct 2012 17:50:14 +0200
> ville.syrjala@linux.intel.com wrote:
> =

> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float
> > format).
> > =

> > Fix intel_init_framebuffer() to match hardware and driver limitations:
> > * RGB332 is not supported at all
> > * CI8 is supported
> > * XRGB1555 & co. are supported on Gen3 and earlier
> > * XRGB210101010 & co. are supported from Gen4 onwards
> > * BGR formats are supported from Gen4 onwards
> > * YUV formats are supported from Gen5 onwards (driver limitation)
> =

> Yeah looks nice.  I love how our definitions have the component order
> reversed relative to the fourcc-ish codes.

Yeah. I just copied the names more or less blindly from the spec. I
usually prefer to keep register definitons and specs in sync, since
it makes it easier to search for stuff in the spec. But if people
are bothered by this mess, I won't object to changing the defns to
match the fourcc stuff.

-- =

Ville Syrj=E4l=E4
Intel OTC