From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 02/11] drm/i915: Add SURFLIVE register
 definitions
Date: Thu, 1 Nov 2012 16:23:29 +0200
Message-ID: <20121101142329.GP3791@intel.com>
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To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Thu, Nov 01, 2012 at 03:19:34PM +0100, Daniel Vetter wrote:
> On Thu, Nov 1, 2012 at 3:16 PM, Ville Syrj=E4l=E4
> <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Oct 31, 2012 at 11:57:00PM +0100, Daniel Vetter wrote:
> >> On Wed, Oct 31, 2012 at 01:23:05PM -0700, Jesse Barnes wrote:
> >> > On Wed, 31 Oct 2012 17:50:15 +0200
> >> > ville.syrjala@linux.intel.com wrote:
> >> >
> >> > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >> > >
> >> > > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >>
> >> Fails to apply here somehow. Also, this thing is base64 encoded, which
> >> confused my normal workflow for a bit ... Dunno what exactly caused th=
is
> >> havoc.
> >
> > Strange. I had it sitting on top of drm-intel-next when I sent it.
> >
> > The whole series seems to be base64 after I got it back from the list.
> > Maybe it's out wonderful mail system trying to do something clever.
> > Base64 itself shouldn't disturb git-am & co.
> =

> Yeah, git am coped fine, but patch was a bit upset. I've then feed it
> the decoded text/plain part, which resulted in some strange conflicts.
> Dunno what has happened there. Can you simply resend a new patch
> rebased on top of latest dinq?

Will do.

-- =

Ville Syrj=E4l=E4
Intel OTC