From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 10/36] drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train Date: Thu, 1 Nov 2012 16:13:44 +0100 Message-ID: <20121101151344.GQ5755@phenom.ffwll.local> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> <1351714375-15284-11-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 005F89E75A for ; Thu, 1 Nov 2012 08:12:37 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id n13so1033357eaa.36 for ; Thu, 01 Nov 2012 08:12:37 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1351714375-15284-11-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 31, 2012 at 06:12:29PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > According to the mode set sequence documentation, this is the right > place. According to the FDI_RX_TUSIZE register description, this is > the value we should set. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_ddi.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 0cb6441..5d33f62 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -196,6 +196,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > > udelay(600); > > + /* Program PCH FDI Receiver TU */ > + I915_WRITE(_FDI_RXA_TUSIZE1, 0x7E000000); > + I think you also want to remove the setting of RX_TU_SIZE in lpt_pch_enable. And we have nice symbolic constants to encode that 0-based 64 shifter by 25 bits ... -Daniel > /* Enable PCH FDI Receiver with auto-training */ > rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; > I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch