From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 16/36] drm/i915: try each voltage twice at hsw_fdi_link_train Date: Thu, 1 Nov 2012 16:16:29 +0100 Message-ID: <20121101151629.GS5755@phenom.ffwll.local> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> <1351714375-15284-17-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 936C59E8D5 for ; Thu, 1 Nov 2012 08:15:23 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so1357662eek.36 for ; Thu, 01 Nov 2012 08:15:22 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1351714375-15284-17-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 31, 2012 at 06:12:35PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > From the mode set sequence document: "Each setting should be tried at > least twice before failing mode set". > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index f8ca3c4..94c6b76 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -179,7 +179,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); > > /* Start the training iterating through available voltages and emphasis */ > - for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) { > + for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { > /* Configure DP_TP_CTL with auto-training */ > I915_WRITE(DP_TP_CTL(PORT_E), > DP_TP_CTL_FDI_AUTOTRAIN | > @@ -191,7 +191,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) > I915_WRITE(DDI_BUF_CTL(PORT_E), > DDI_BUF_CTL_ENABLE | > ((intel_crtc->fdi_lanes - 1) << 1) | > - hsw_ddi_buf_ctl_values[i]); > + hsw_ddi_buf_ctl_values[i >> 1]); I think a simple / 2 is clearer here and symmetric with the * 2 above. The compiler will apply clever tricks for you anyway ;-) -Daniel > POSTING_READ(DDI_BUF_CTL(PORT_E)); > > udelay(600); > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch