From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 19/36] drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll Date: Thu, 1 Nov 2012 16:40:53 +0100 Message-ID: <20121101154053.GW5755@phenom.ffwll.local> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> <1351714375-15284-20-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A0329E9AB for ; Thu, 1 Nov 2012 08:39:46 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id n13so1043278eaa.36 for ; Thu, 01 Nov 2012 08:39:46 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1351714375-15284-20-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 31, 2012 at 06:12:38PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because this function is only for the older PCHs, not the newer ones. > > Signed-off-by: Paulo Zanoni Ok, I've merged patches 1-6 plus this one here for now. gtg, will resume reviewing afterwards. Thanks a lot for digging through this mess. Cheers, Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f9441d1..39f5bd1 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1579,14 +1579,14 @@ out_unlock: > } > > /** > - * intel_enable_pch_pll - enable PCH PLL > + * ironlake_enable_pch_pll - enable PCH PLL > * @dev_priv: i915 private structure > * @pipe: pipe PLL to enable > * > * The PCH PLL needs to be enabled before the PCH transcoder, since it > * drives the transcoder clock. > */ > -static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) > +static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) > { > struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; > struct intel_pch_pll *pll; > @@ -3053,7 +3053,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > * Note that enable_pch_pll tries to do the right thing, but get_pch_pll > * unconditionally resets the pll - we need that to have the right LVDS > * enable sequence. */ > - intel_enable_pch_pll(intel_crtc); > + ironlake_enable_pch_pll(intel_crtc); > > if (HAS_PCH_CPT(dev)) { > u32 sel; > @@ -3149,7 +3149,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) > * Note that enable_pch_pll tries to do the right thing, but get_pch_pll > * unconditionally resets the pll - we need that to have the right LVDS > * enable sequence. */ > - intel_enable_pch_pll(intel_crtc); > + ironlake_enable_pch_pll(intel_crtc); > > lpt_program_iclkip(crtc); > > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch