From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder Date: Thu, 1 Nov 2012 17:16:11 +0100 Message-ID: <20121101161611.GY5755@phenom.ffwll.local> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> <1351714375-15284-30-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 07CCC9EB47 for ; Thu, 1 Nov 2012 09:15:05 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id n13so1058147eaa.36 for ; Thu, 01 Nov 2012 09:15:04 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1351714375-15284-30-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > ... instead of PIPECONF_INTERLACE_MASK. > > Signed-off-by: Paulo Zanoni My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch, but everything with bit 23 set is a reserved value. Sinc we set the correct stuff anyway, I don't think we need to change the mask here - the same would apply to cpt. So I'll drop this one here. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 066994f..4fbb296 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, > pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); > > val &= ~TRANS_INTERLACE_MASK; > - if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) > + if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == > + PIPECONF_INTERLACED_ILK) > val |= TRANS_INTERLACED; > else > val |= TRANS_PROGRESSIVE; > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch