From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] drm/i915: Handle sync_seqno correctly when seqno has wrapped. Date: Tue, 13 Nov 2012 08:52:59 -0800 Message-ID: <20121113085259.448df5cb@bwidawsk.net> References: <1352814696-2154-1-git-send-email-mika.kuoppala@intel.com> <20121113083926.340d40d5@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id B46C39E946 for ; Tue, 13 Nov 2012 08:53:14 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 13 Nov 2012 17:45:14 +0100 Daniel Vetter wrote: > On Tue, Nov 13, 2012 at 5:39 PM, Ben Widawsky wrote: > > > > Also as an overall comment, I want the patches to guarantee to catch > > the bug you found, which I think with the randomness of > > gem_stress - isn't. Specifically, we want the waiting ring to be > > waiting on a pre-wrapped value. Maybe I missed that guarantee, but if > > there is a quick/dirty way to make that happen, that would better than > > running an arbitrary number of gem_stress tests. > > I think running just gem_stress is ok - as long as the test has a > reasonable good chance of blowing up. On future platforms something > else than semaphores might blow up, or we might simply botch a seqno > comparison. So imo having a test that just beats a bit on the > systems+the wrap-around after each boot/resume should give us > excellent coverage, and trying to engineer a perfect test for the > single failure mode we now have in front of us might actually reduce > coverage. > -Daniel I didn't say don't run gem_stress... -- Ben Widawsky, Intel Open Source Technology Center