From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: drop buggy write to
 FDI_RX_CHICKEN register
Date: Thu, 15 Nov 2012 14:22:27 +0100
Message-ID: <20121115132227.GW5854@phenom.ffwll.local>
References: <1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>, Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Thu, Nov 15, 2012 at 10:42:02AM +0000, Chris Wilson wrote:
> On Wed, 14 Nov 2012 17:47:39 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Jani Nikula noticed that the parentheses are wrong and we & the bit
> > with the register address instead of the read-back value. He sent a
> > patch to correct that.
> > 
> > On second look, we write the same register in the previous line, and
> > the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the
> > logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle
> > ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder.
> > 
> > So the right things seems to be to simply kill the 2nd write.
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Looks sane(r).
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch