From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 06/10] drm/i915: check the power down well on assert_pipe() Date: Mon, 21 Jan 2013 15:45:48 +0200 Message-ID: <20130121134548.GC9135@intel.com> References: <1358540953-3979-1-git-send-email-przanoni@gmail.com> <1358540953-3979-7-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 2368EE6465 for ; Mon, 21 Jan 2013 05:45:52 -0800 (PST) Content-Disposition: inline In-Reply-To: <1358540953-3979-7-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Jan 18, 2013 at 06:29:08PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > = > If the power well is disabled, we should not try to read its > registers, otherwise we'll get "unclaimed register" messages. > = > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index a7fb7e1..921b020 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1214,9 +1214,15 @@ void assert_pipe(struct drm_i915_private *dev_priv, > if (pipe =3D=3D PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) > state =3D true; > = > - reg =3D PIPECONF(cpu_transcoder); > - val =3D I915_READ(reg); > - cur_state =3D !!(val & PIPECONF_ENABLE); > + if (cpu_transcoder =3D=3D TRANSCODER_EDP || > + (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE)) { Should that also check HSW_PWR_WELL_ENABLE? KVMR might have the well enabled, while the driver has it disabled. But KVMR might have already disabled the well, and it might get disabled just after this check, and then you would hit the unclaimed register issue again. > + reg =3D PIPECONF(cpu_transcoder); > + val =3D I915_READ(reg); > + cur_state =3D !!(val & PIPECONF_ENABLE); > + } else { > + cur_state =3D false; > + } > + > WARN(cur_state !=3D state, > "pipe %c assertion failure (expected %s, current %s)\n", > pipe_name(pipe), state_string(state), state_string(cur_state)); > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC