Re: [PATCH 06/10] drm/i915: check the power down well on assert_pipe()

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Jan 22, 2013 at 02:04:09PM +0100, Daniel Vetter wrote:
> On Mon, Jan 21, 2013 at 03:45:48PM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 18, 2013 at 06:29:08PM -0200, Paulo Zanoni wrote:
> > > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > 
> > > If the power well is disabled, we should not try to read its
> > > registers, otherwise we'll get "unclaimed register" messages.
> > > 
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c |   12 +++++++++---
> > >  1 file changed, 9 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index a7fb7e1..921b020 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -1214,9 +1214,15 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> > >  	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
> > >  		state = true;
> > >  
> > > -	reg = PIPECONF(cpu_transcoder);
> > > -	val = I915_READ(reg);
> > > -	cur_state = !!(val & PIPECONF_ENABLE);
> > > +	if (cpu_transcoder == TRANSCODER_EDP ||
> > > +	    (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE)) {
> > 
> > Should that also check HSW_PWR_WELL_ENABLE? KVMR might have the well
> > enabled, while the driver has it disabled. But KVMR might have already
> > disabled the well, and it might get disabled just after this check,
> > and then you would hit the unclaimed register issue again.
> 
> The important matter is to not read registers in the power well if it's
> off, for which checking just one of the three bits is enough. If the kvm
> keeps the power well on, we just avoid checking the pipe state if we don't
> need the power well, but otherwise no side effect. Otoh just one set bit
> makes sure that the power well is on and we can read the regs).

The power well may be on when you're reading the status bit, but
assuming it was KVMR who caused the power well to be powered on,
we can't be sure the power well will remain powered long enough
to read the registers.

-- 
Ville Syrjälä
Intel OTC