From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers Date: Thu, 24 Jan 2013 23:26:10 +0100 Message-ID: <20130124222610.GE23080@phenom.ffwll.local> References: <1359034198-19678-1-git-send-email-ville.syrjala@linux.intel.com> <1359034198-19678-25-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f43.google.com (mail-ee0-f43.google.com [74.125.83.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 48D9FE6C9E for ; Thu, 24 Jan 2013 14:24:05 -0800 (PST) Received: by mail-ee0-f43.google.com with SMTP id c50so4997797eek.2 for ; Thu, 24 Jan 2013 14:24:04 -0800 (PST) Content-Disposition: inline In-Reply-To: <1359034198-19678-25-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 24, 2013 at 03:29:49PM +0200, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths. > = > Signed-off-by: Ville Syrj=E4l=E4 By sheer coincidence I'm working on a few patches to no longer safe/restore the legacy vga regs for DRIVER_MODESET. Which means this here isn't required any more. For the current wip: http://cgit.freedesktop.org/~danvet/drm/log/?h=3Dmodeset_s-r -Daniel > --- > drivers/gpu/drm/i915/i915_suspend.c | 20 ++++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i= 915_suspend.c > index 63d4d30..05d82dc 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -691,9 +691,11 @@ static void i915_save_display(struct drm_device *dev) > } > = > /* VGA state */ > - dev_priv->regfile.saveVGA0 =3D I915_READ(VGA0); > - dev_priv->regfile.saveVGA1 =3D I915_READ(VGA1); > - dev_priv->regfile.saveVGA_PD =3D I915_READ(VGA_PD); > + if (!IS_VALLEYVIEW(dev)) { > + dev_priv->regfile.saveVGA0 =3D I915_READ(VGA0); > + dev_priv->regfile.saveVGA1 =3D I915_READ(VGA1); > + dev_priv->regfile.saveVGA_PD =3D I915_READ(VGA_PD); > + } > if (HAS_PCH_SPLIT(dev)) > dev_priv->regfile.saveVGACNTRL =3D I915_READ(CPU_VGACNTRL); > else > @@ -793,11 +795,13 @@ static void i915_restore_display(struct drm_device = *dev) > else > I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL); > = > - I915_WRITE(VGA0, dev_priv->regfile.saveVGA0); > - I915_WRITE(VGA1, dev_priv->regfile.saveVGA1); > - I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD); > - POSTING_READ(VGA_PD); > - udelay(150); > + if (!IS_VALLEYVIEW(dev)) { > + I915_WRITE(VGA0, dev_priv->regfile.saveVGA0); > + I915_WRITE(VGA1, dev_priv->regfile.saveVGA1); > + I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD); > + POSTING_READ(VGA_PD); > + udelay(150); > + } > = > i915_restore_vga(dev); > } > -- = > 1.7.12.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch