From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 29/33] drm/i915: VGA registers need an
 offset on VLV
Date: Fri, 25 Jan 2013 12:27:54 +0200
Message-ID: <20130125102754.GP9135@intel.com>
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To: Daniel Vetter <daniel@ffwll.ch>
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On Thu, Jan 24, 2013 at 11:44:09PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> Admittedly I haven't checked them closely, but with my proposed patch in
> he modeset_s-r branch, do we still need to adjust these? I kinda don't
> want to keep the legacy vga plane registers around ...

I found two exceptions, well, one really.

i915_disable_vga() pokes at one sequencer register.

intel_crt_load_detect() polls the sense bit in ST00, but I don't think
we should ever go there w/ VLV due to is_hotplug=3D1.

-- =

Ville Syrj=E4l=E4
Intel OTC