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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV
Date: Fri, 25 Jan 2013 12:57:39 +0200	[thread overview]
Message-ID: <20130125105739.GS9135@intel.com> (raw)
In-Reply-To: <20130124222215.GD23080@phenom.ffwll.local>

On Thu, Jan 24, 2013 at 11:22:15PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I've noticed that the PALETTE moved around a bit for pch-split platforms
> already, but otoh the palette support is quite enhanced there already, and
> we don't bother with it. Which renders 10bpc a bit pointless. So I'll gulp
> this one here.

Yeah we really need to revamp the palette/gamma code at some
point.

I think what we used to have on older hardware was 8bit LUT or
10bit interpolated ramp. And on more recent hardware we have
8bit LUT, 10bit LUT, or 12bit interpolated ramp. And currently
we only use the 8bit LUT.

> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 15ecded..7c71622 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1169,8 +1169,8 @@
> >   * Palette regs
> >   */
> >  
> > -#define _PALETTE_A		0x0a000
> > -#define _PALETTE_B		0x0a800
> > +#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
> > +#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
> >  #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
> >  
> >  /* MCH MMIO space */
> > -- 
> > 1.7.12.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-01-25 10:57 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
2013-01-24 17:49   ` Paulo Zanoni
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
2013-01-24 17:54   ` Paulo Zanoni
2013-01-25 12:28     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info ville.syrjala
2013-01-24 13:29 ` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only ville.syrjala
2013-01-24 13:29 ` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is " ville.syrjala
2013-01-24 13:29 ` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
2013-01-24 21:37   ` Daniel Vetter
2013-01-25 12:26     ` Ville Syrjälä
2013-01-25 16:21       ` Daniel Vetter
2013-01-26 16:41         ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
2013-01-24 21:39   ` Daniel Vetter
2013-01-25 12:21     ` Ville Syrjälä
2013-01-25 16:00       ` Daniel Vetter
2013-01-25 16:22         ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 10/33] drm/i915: Primary plane registers need " ville.syrjala
2013-01-24 13:29 ` [PATCH 11/33] drm/i915: Pipe " ville.syrjala
2013-01-24 13:29 ` [PATCH 12/33] drm/i915: Cursor " ville.syrjala
2013-01-24 13:29 ` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
2013-01-24 22:01   ` Daniel Vetter
2013-01-25 12:05     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
2013-01-24 22:05   ` Daniel Vetter
2013-01-25 12:03     ` Ville Syrjälä
2013-01-25 16:02       ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 18/33] drm/i915: Panel fitter registers need an offset " ville.syrjala
2013-01-24 13:29 ` [PATCH 19/33] drm/i915: PORT_HOTPLUG " ville.syrjala
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
2013-01-24 22:12   ` Daniel Vetter
2013-01-25 11:59     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
2013-01-24 22:22   ` Daniel Vetter
2013-01-25 10:57     ` Ville Syrjälä [this message]
2013-01-24 13:29 ` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
2013-01-24 22:26   ` Daniel Vetter
2013-01-25 10:51     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
2013-01-24 22:41   ` Daniel Vetter
2013-01-25 10:51     ` Ville Syrjälä
2013-01-25 16:06       ` Daniel Vetter
2013-01-25 16:20         ` Ville Syrjälä
2013-01-25 16:24           ` Daniel Vetter
2013-01-25 16:28           ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable ville.syrjala
2013-01-24 13:29 ` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers ville.syrjala
2013-01-24 13:29 ` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
2013-01-24 22:44   ` Daniel Vetter
2013-01-25 10:27     ` Ville Syrjälä
2013-01-25 16:18       ` Daniel Vetter
2013-01-25 16:24         ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 30/33] drm/i915: GPIO/GMBUS " ville.syrjala
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
2013-01-24 22:59   ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers ville.syrjala

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