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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/33] drm/i915: Convert intel_dp to enum port
Date: Fri, 25 Jan 2013 14:28:35 +0200	[thread overview]
Message-ID: <20130125122835.GY9135@intel.com> (raw)
In-Reply-To: <CA+gsUGTAzxDTeQ8RZR+qipDVurkouSatHpCUJUnwqCqv2f2jsA@mail.gmail.com>

On Thu, Jan 24, 2013 at 03:54:19PM -0200, Paulo Zanoni wrote:
> Hi
> 
> 2013/1/24  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use intel_dig_port->port rather than intel_dp->output_reg.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f05364a..d274f8e 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2293,16 +2293,17 @@ g4x_dp_detect(struct intel_dp *intel_dp)
> >  {
> >         struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > +       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 
> 
> Minor optional detail:
> With "struct drm_device *dev = intel_dig_port->base.base.dev" you
> would save a call to intel_dp_to_dev (which calls dp_to_dig_port).

Dang :)

> With or without that:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Cheers. Daniel slurped it already, so w/o it is.

> 
> >         uint32_t bit;
> >
> > -       switch (intel_dp->output_reg) {
> > -       case DP_B:
> > +       switch (intel_dig_port->port) {
> > +       case PORT_B:
> >                 bit = DPB_HOTPLUG_LIVE_STATUS;
> >                 break;
> > -       case DP_C:
> > +       case PORT_C:
> >                 bit = DPC_HOTPLUG_LIVE_STATUS;
> >                 break;
> > -       case DP_D:
> > +       case PORT_D:
> >                 bit = DPD_HOTPLUG_LIVE_STATUS;
> >                 break;
> >         default:
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-01-25 12:28 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
2013-01-24 17:49   ` Paulo Zanoni
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
2013-01-24 17:54   ` Paulo Zanoni
2013-01-25 12:28     ` Ville Syrjälä [this message]
2013-01-24 13:29 ` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info ville.syrjala
2013-01-24 13:29 ` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only ville.syrjala
2013-01-24 13:29 ` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is " ville.syrjala
2013-01-24 13:29 ` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
2013-01-24 21:37   ` Daniel Vetter
2013-01-25 12:26     ` Ville Syrjälä
2013-01-25 16:21       ` Daniel Vetter
2013-01-26 16:41         ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
2013-01-24 21:39   ` Daniel Vetter
2013-01-25 12:21     ` Ville Syrjälä
2013-01-25 16:00       ` Daniel Vetter
2013-01-25 16:22         ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 10/33] drm/i915: Primary plane registers need " ville.syrjala
2013-01-24 13:29 ` [PATCH 11/33] drm/i915: Pipe " ville.syrjala
2013-01-24 13:29 ` [PATCH 12/33] drm/i915: Cursor " ville.syrjala
2013-01-24 13:29 ` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
2013-01-24 22:01   ` Daniel Vetter
2013-01-25 12:05     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
2013-01-24 22:05   ` Daniel Vetter
2013-01-25 12:03     ` Ville Syrjälä
2013-01-25 16:02       ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 18/33] drm/i915: Panel fitter registers need an offset " ville.syrjala
2013-01-24 13:29 ` [PATCH 19/33] drm/i915: PORT_HOTPLUG " ville.syrjala
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
2013-01-24 22:12   ` Daniel Vetter
2013-01-25 11:59     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
2013-01-24 22:22   ` Daniel Vetter
2013-01-25 10:57     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
2013-01-24 22:26   ` Daniel Vetter
2013-01-25 10:51     ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
2013-01-24 22:41   ` Daniel Vetter
2013-01-25 10:51     ` Ville Syrjälä
2013-01-25 16:06       ` Daniel Vetter
2013-01-25 16:20         ` Ville Syrjälä
2013-01-25 16:24           ` Daniel Vetter
2013-01-25 16:28           ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable ville.syrjala
2013-01-24 13:29 ` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers ville.syrjala
2013-01-24 13:29 ` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
2013-01-24 22:44   ` Daniel Vetter
2013-01-25 10:27     ` Ville Syrjälä
2013-01-25 16:18       ` Daniel Vetter
2013-01-25 16:24         ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 30/33] drm/i915: GPIO/GMBUS " ville.syrjala
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
2013-01-24 22:59   ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers ville.syrjala

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