From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 25/33] drm/i915: PLL and clock gating
 registers need an offset on VLV
Date: Fri, 25 Jan 2013 18:28:24 +0200
Message-ID: <20130125162824.GI9135@intel.com>
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To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Jan 25, 2013 at 06:20:53PM +0200, Ville Syrj=E4l=E4 wrote:
> On Fri, Jan 25, 2013 at 05:06:51PM +0100, Daniel Vetter wrote:
> > On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrj=E4l=E4 wrote:
> > > On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > > > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel=
.com wrote:
> > > > >  #define  DSTATE_GFX_RESET_I830			(1<<6)
> > > > >  #define  DSTATE_PLL_D3_OFF			(1<<3)
> > > > >  #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
> > > > >  #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
> > > > > -#define DSPCLK_GATE_D		0x6200
> > > > > +#define DSPCLK_GATE_D		(dev_priv->info->display_mmio_offset + 0x=
6200)
> > > > =

> > > > This one here seems to be only used up to gen4 ...
> > > =

> > > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> > > same code commented out, so it may be that we can skip it too. Anyone
> > > have more details on this quirk?
> > =

> > Afaict that quirk is for pnv only.
> =

> So, should we just kill it for other HW? At least it needs to be killed
> for VLV if we don't merge this hunk.

Ah, it already is disabled for everything else. Great, less work for
me.

-- =

Ville Syrj=E4l=E4
Intel OTC