From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] drm/i915: implement MCH pipe underrun prevention for snb/ivb Date: Thu, 7 Feb 2013 10:09:07 -0800 Message-ID: <20130207180907.GA723@lundgren.nims.intel.com> References: <1360247004-15707-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E246E6350 for ; Thu, 7 Feb 2013 10:07:56 -0800 (PST) Content-Disposition: inline In-Reply-To: <1360247004-15707-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development , "Runyan, Arthur J" List-Id: intel-gfx@lists.freedesktop.org On Thu, Feb 07, 2013 at 03:23:24PM +0100, Daniel Vetter wrote: > Some early bios versions seem to ship with the wrong tuning values for > the MCH, possible resulting in pipe underruns under load. Especially > on DP outputs this can lead to black screen, since DP really doesn't > like an occasional whack from an underrun. > > Unfortunately the registers seem to be locked after boot, so the only > thing we can do is politely point out issues and suggest a BIOS > upgrade. > > Arthur Runyan pointed us at this issue while discussion DP bugs - thus > far no confirmation from a bug report yet that it helps. But at least > some of my machines here have wrong values, so this might be useful in > understanding bug reports. > > Cc: Runyan, Arthur J > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8754f91..b3915cf 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1235,6 +1235,14 @@ > #define MAD_DIMM_A_SIZE_SHIFT 0 > #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) > > +/** snb MCH registers for priority tuning */ > +#define MCH_TC_RFP_C0 (MCHBAR_MIRROR_BASE_SNB + 0x4294) > +#define MCH_TC_RFP_C1 (MCHBAR_MIRROR_BASE_SNB + 0x4694) > +#define TC_RFP_OREF_MASK 0xff > +#define TC_RFP_OREF_VAL 0xff > +#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) > +#define MCH_SSKPD_WM0_MASK 0x3f > +#define MCH_SSKPD_WM0_VAL 0xc According to the bug report I'm reading, there are several valid values, so I think you should do some more work. [snip] -- Ben Widawsky, Intel Open Source Technology Center