From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/6] drm/i915: Don't wait for page flips if there was GPU reset Date: Wed, 13 Feb 2013 18:09:48 +0100 Message-ID: <20130213170947.GN5813@phenom.ffwll.local> References: <1359476018-31274-1-git-send-email-ville.syrjala@linux.intel.com> <1359476018-31274-3-git-send-email-ville.syrjala@linux.intel.com> <20130213152326.GJ5813@phenom.ffwll.local> <20130213165229.GP9135@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f43.google.com (mail-ee0-f43.google.com [74.125.83.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 900CBE5EA7 for ; Wed, 13 Feb 2013 09:07:33 -0800 (PST) Received: by mail-ee0-f43.google.com with SMTP id c50so776066eek.2 for ; Wed, 13 Feb 2013 09:07:32 -0800 (PST) Content-Disposition: inline In-Reply-To: <20130213165229.GP9135@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Feb 13, 2013 at 06:52:29PM +0200, Ville Syrj=E4l=E4 wrote: > On Wed, Feb 13, 2013 at 04:23:27PM +0100, Daniel Vetter wrote: > > On Tue, Jan 29, 2013 at 06:13:34PM +0200, ville.syrjala@linux.intel.com= wrote: > > > From: Ville Syrj=E4l=E4 > > > = > > > If a GPU reset occurs while a page flip has been submitted to the rin= g, > > > the flip will never complete once the ring has been reset. > > > = > > > The GPU reset can be detected by sampling the reset_counter before the > > > flip is submitted, and then while waiting for the flip, the sampled > > > counter is compared with the current reset_counter value. > > > = > > > Signed-off-by: Ville Syrj=E4l=E4 > > > --- > > > drivers/gpu/drm/i915/intel_display.c | 14 +++++++++++++- > > > drivers/gpu/drm/i915/intel_drv.h | 3 +++ > > > 2 files changed, 16 insertions(+), 1 deletion(-) > > > = > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i= 915/intel_display.c > > > index 4097118..e348a68 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -2862,10 +2862,12 @@ static bool intel_crtc_has_pending_flip(struc= t drm_crtc *crtc) > > > { > > > struct drm_device *dev =3D crtc->dev; > > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > > unsigned long flags; > > > bool pending; > > > = > > > - if (i915_reset_in_progress(&dev_priv->gpu_error)) > > > + if (i915_reset_in_progress(&dev_priv->gpu_error) || > > > + intel_crtc->reset_counter !=3D atomic_read(&dev_priv->gpu_error= .reset_counter)) > > > return false; > > > = > > > spin_lock_irqsave(&dev->event_lock, flags); > > > @@ -6912,6 +6914,8 @@ static int intel_gen2_queue_flip(struct drm_dev= ice *dev, > > > if (ret) > > > goto err_unpin; > > > = > > > + intel_crtc->reset_counter =3D atomic_read(&dev_priv->gpu_error.rese= t_counter); > > = > > Ok no bikeshed about ->reset_counter, but a different one: Why does this > > need to be in the per-gen callback? Can't we just grab this before we c= all > > down into these callbacks? Imo races wrt the reset/hang code don't matt= er > > that much as long as we don't wait forever for a pageflip which won't > > happen. Hanging the gpu concurrently to pageflipping is undefined anyway > > right now ... > = > Yeah. It could be moved to happen a little earlier, and thus avoid the > duplication. Applied the patch and moved the assignment around a bit, thanks. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch