From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Turn off hsync and vsync on ADPA when disabling crt Date: Tue, 5 Mar 2013 16:23:59 +0100 Message-ID: <20130305152359.GH9021@phenom.ffwll.local> References: <1362489888-32651-1-git-send-email-patrik.r.jakobsson@gmail.com> <20130305134530.GU4469@intel.com> <20130305145912.GW4469@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f44.google.com (mail-wg0-f44.google.com [74.125.82.44]) by gabe.freedesktop.org (Postfix) with ESMTP id B348DE5F0A for ; Tue, 5 Mar 2013 07:21:27 -0800 (PST) Received: by mail-wg0-f44.google.com with SMTP id dr12so5908606wgb.35 for ; Tue, 05 Mar 2013 07:21:26 -0800 (PST) Content-Disposition: inline In-Reply-To: <20130305145912.GW4469@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Mar 05, 2013 at 04:59:12PM +0200, Ville Syrj=E4l=E4 wrote: > On Tue, Mar 05, 2013 at 03:33:26PM +0100, Patrik Jakobsson wrote: > > > Accroding to the docs these bits don't exist on PCH platforms. > > > intel_crt_dpms() already has a check for this, so I suppose > > > intel_disable_crt() should have one too. > > > > > > Also I noticed that we seem to have the hsync and vsync disable > > > bits reversed. At least that's what the docs are telling me. > > = > > The PCH check just forces suspend and standby to off and we're only doi= ng dpms > > off in intel_disable_crt() so no need to check it there. > = > You're right. I assumed that the check would somehow avoid setting > these bits too, but it doesn't. So I guess we don't really care > that they don't exist. The dpms state gets clamped to the values support by the hw in intel_crt_dpms. So I think we should care also in intel_crt_disable. > > I'm looking at the 965/G35 PRM and the "sync disable" are defined corre= ctly but > > used incorrectly in intel_disable_crt(). That's what my patch fixes. I = haven't > > checked the other PRMs. Is it different on newer hardware? > = > This is what the docs say: > = > 11:10 Monitor DPMS: (for CRT port) ... > ... > 00 =3D ... (will not affect sync pulses) > 01 =3D ... (HSYNC pulses, VSYNC does not) > 10 =3D ... (VSYNC pulses, HSYNC does not) > 11 =3D ... (Neither HSYNC nor VSYNC pulses) > = > These are our definintions: > = > #define ADPA_VSYNC_CNTL_DISABLE (1<<11) > #define ADPA_HSYNC_CNTL_DISABLE (1<<10) > = > As you can see they don't match. I've checked gen2/3 docs and they agree with this, so we need to update the #define. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch