From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 04/15] drm/i915: don't touch the PF regs if the power well is down Date: Thu, 7 Mar 2013 00:28:32 +0100 Message-ID: <20130306232832.GF9021@phenom.ffwll.local> References: <1362611003-4823-1-git-send-email-przanoni@gmail.com> <1362611003-4823-5-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 2ACE2E5CD5 for ; Wed, 6 Mar 2013 15:26:00 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id d41so6065440eek.36 for ; Wed, 06 Mar 2013 15:25:59 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362611003-4823-5-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 06, 2013 at 08:03:11PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > This solves some "unclaimed register" messages when booting the > machine with eDP attached. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index bd27336..9a9f6d7 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3584,8 +3584,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); > > /* Disable PF */ > - I915_WRITE(PF_CTL(pipe), 0); > - I915_WRITE(PF_WIN_SZ(pipe), 0); > + if (!intel_power_well_is_down(dev)) { > + I915_WRITE(PF_CTL(pipe), 0); > + I915_WRITE(PF_WIN_SZ(pipe), 0); > + } I'd vote for a /* XXX: Once we have proper pfit state tracking implemented with hw state read/check support we should switch to only disable the pfit when we know it's used */ The idea is that the power well code here irks me a bit, after all if something is on and we want to disable it, it can't be also off due to the power well being down ;-) -Daniel > > intel_ddi_disable_pipe_clock(intel_crtc); > > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch