From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 07/15] drm/i915: there's no DSPADDR register on Haswell Date: Fri, 15 Mar 2013 12:10:02 -0700 Message-ID: <20130315191001.GI17773@bwidawsk.net> References: <1362611003-4823-1-git-send-email-przanoni@gmail.com> <1362611003-4823-8-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.localdomain (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 99093E6AF0 for ; Fri, 15 Mar 2013 12:10:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1362611003-4823-8-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 06, 2013 at 08:03:14PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > So don't read it when we hang the GPU. This solves "unclaimed > register" messages. > > Signed-off-by: Paulo Zanoni It would be nice if you could make this a bit more future proof, but looks correct to me: Reviewed-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 56cca6e..0451056 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9351,7 +9351,8 @@ intel_display_capture_error_state(struct drm_device *dev) > if (INTEL_INFO(dev)->gen <= 3) > error->plane[i].size = I915_READ(DSPSIZE(i)); > error->plane[i].pos = I915_READ(DSPPOS(i)); > - error->plane[i].addr = I915_READ(DSPADDR(i)); > + if (!IS_HASWELL(dev)) > + error->plane[i].addr = I915_READ(DSPADDR(i)); > if (INTEL_INFO(dev)->gen >= 4) { > error->plane[i].surface = I915_READ(DSPSURF(i)); > error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); > @@ -9396,7 +9397,8 @@ intel_display_print_error_state(struct seq_file *m, > if (INTEL_INFO(dev)->gen <= 3) > seq_printf(m, " SIZE: %08x\n", error->plane[i].size); > seq_printf(m, " POS: %08x\n", error->plane[i].pos); > - seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); > + if (!IS_HASWELL(dev)) > + seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); > if (INTEL_INFO(dev)->gen >= 4) { > seq_printf(m, " SURF: %08x\n", error->plane[i].surface); > seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center