From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 08/15] drm/i915: remove DSPPOS register
Date: Sun, 17 Mar 2013 21:39:29 +0100
Message-ID: <20130317203929.GO9021@phenom.ffwll.local>
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To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Thu, Mar 07, 2013 at 11:43:14AM +0200, Ville Syrj=E4l=E4 wrote:
> On Wed, Mar 06, 2013 at 08:03:15PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > =

> > I couldn't find any evidence that this register exists on Gen2+. On
> > Gen 2/3/4 documents this register is listed as reserved and read-only.
> > On the newer Gens this register is not even documented.
> =

> DSPPOS goes hand in hand with DSPSIZE. IIRC DSPA never had the
> windowing capability, but DSPB and DSPC on older gens had it.

Indeed Ville's right here, gen2/3 have this on sprite B/C (you could move
those things around back then to different pipes ...). So I think we want
a gen <=3D 3 check here (gen4+ lost this apparently with the fixed
pipe->plane mapping).
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch