From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 7/9] drm/i915: Don't wait for PCH on reset
Date: Tue, 19 Mar 2013 12:36:04 -0700
Message-ID: <20130319123604.13cc6317@jbarnes-desktop>
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To: Ben Widawsky <ben@bwidawsk.net>
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	Jeffrey" <jeffrey.mcallister@intel.com>
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On Wed, 13 Mar 2013 11:21:06 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> BIOS should be setting this, but in case it doesn't...
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1417fc6..ee9c14c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3986,6 +3986,9 @@ i915_gem_init_hw(struct drm_device *dev)
>  	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
>  		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
>  
> +	if (HAS_PCH_NOP(dev))
> +		I915_WRITE(GEN7_MSG_CTL, 0);
> +
>  	i915_gem_l3_remap(dev);
>  
>  	i915_gem_init_swizzling(dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4cf3ece..00b6a55 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3481,6 +3481,7 @@
>  #define DISP_ARB_CTL	0x45000
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
> +#define GEN7_MSG_CTL	0x45010
>  
>  /* GEN7 chicken */
>  #define GEN7_COMMON_SLICE_CHICKEN1		0x7010

I think this needs a comment or at least a define or two for the bits.
And are we sure we want to clobber the upper bits?  They're listed as
"PBC", which may be related to PBR, but somehow I doubt the GT will
spew beer if we write the bits.

-- 
Jesse Barnes, Intel Open Source Technology Center