From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: Don't overclock on Haswell Date: Mon, 25 Mar 2013 07:36:51 -0700 Message-ID: <20130325073651.6b9b9202@jbarnes-desktop> References: <1363749596-1429-1-git-send-email-ben@bwidawsk.net> <1364085991-20495-1-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.bluehost.com (unknown [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id 6554BE5C86 for ; Mon, 25 Mar 2013 07:36:59 -0700 (PDT) In-Reply-To: <1364085991-20495-1-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 23 Mar 2013 17:46:31 -0700 Ben Widawsky wrote: > HSW doesn't overclock the same way as IVB or SNB. I do not know about > VLV, so I've kept that off as well. I'm still working on getting the doc > updates to explain how we overclock on Haswell. > > Cc: Jesse Barnes > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ce3db2c..9c11dd9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2628,7 +2628,7 @@ static void gen6_enable_rps(struct drm_device *dev) > (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); > > ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); > - if (!ret) { > + if (!ret && IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { > pcu_mbox = 0; > ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); > if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ This won't affect VLV, since I have a new rps enable function in my latest set. But it looks fine. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center