From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Don't overclock on Haswell
Date: Mon, 25 Mar 2013 16:38:24 +0100
Message-ID: <20130325153824.GK9021@phenom.ffwll.local>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Ben Widawsky <ben@bwidawsk.net>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Mon, Mar 25, 2013 at 07:36:51AM -0700, Jesse Barnes wrote:
> On Sat, 23 Mar 2013 17:46:31 -0700
> Ben Widawsky <ben@bwidawsk.net> wrote:
> 
> > HSW doesn't overclock the same way as IVB or SNB. I do not know about
> > VLV, so I've kept that off as well. I'm still working on getting the doc
> > updates to explain how we overclock on Haswell.
> > 
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ce3db2c..9c11dd9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2628,7 +2628,7 @@ static void gen6_enable_rps(struct drm_device *dev)
> >  		   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
> >  
> >  	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
> > -	if (!ret) {
> > +	if (!ret && IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> >  		pcu_mbox = 0;
> >  		ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
> >  		if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
> 
> This won't affect VLV, since I have a new rps enable function in my
> latest set.  But it looks fine.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch