From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2 Date: Tue, 2 Apr 2013 20:49:42 +0200 Message-ID: <20130402184942.GA2228@phenom.ffwll.local> References: <1364489747-2050-1-git-send-email-jbarnes@virtuousgeek.org> <1364489747-2050-4-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id C4421E61C9 for ; Tue, 2 Apr 2013 11:46:46 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id d41so375909eek.8 for ; Tue, 02 Apr 2013 11:46:46 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1364489747-2050-4-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Mar 28, 2013 at 09:55:40AM -0700, Jesse Barnes wrote: > Needed to handle pre/post enable/disable paths on VLV and avoid a few > fields that are marked reserved on VLV. > > v2: don't set color range or DP PLL fields (Jani) > > Signed-off-by: Jesse Barnes This maze of platform checks in our DP code is getting messy. Still, queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/intel_dp.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 2f2ec42..7fb9213 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -941,7 +941,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, > else > intel_dp->DP |= DP_PLL_FREQ_270MHZ; > } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { > - if (!HAS_PCH_SPLIT(dev)) > + if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) > intel_dp->DP |= intel_dp->color_range; > > if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) > @@ -956,7 +956,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, > if (intel_crtc->pipe == 1) > intel_dp->DP |= DP_PIPEB_SELECT; > > - if (is_cpu_edp(intel_dp)) { > + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { > /* don't miss out required setting for eDP */ > if (adjusted_mode->clock < 200000) > intel_dp->DP |= DP_PLL_FREQ_160MHZ; > @@ -1388,10 +1388,12 @@ static void intel_disable_dp(struct intel_encoder *encoder) > static void intel_post_disable_dp(struct intel_encoder *encoder) > { > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > + struct drm_device *dev = encoder->base.dev; > > if (is_cpu_edp(intel_dp)) { > intel_dp_link_down(intel_dp); > - ironlake_edp_pll_off(intel_dp); > + if (!IS_VALLEYVIEW(dev)) > + ironlake_edp_pll_off(intel_dp); > } > } > > @@ -1417,8 +1419,9 @@ static void intel_enable_dp(struct intel_encoder *encoder) > static void intel_pre_enable_dp(struct intel_encoder *encoder) > { > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > + struct drm_device *dev = encoder->base.dev; > > - if (is_cpu_edp(intel_dp)) > + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) > ironlake_edp_pll_on(intel_dp); > } > > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch