From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf() Date: Wed, 3 Apr 2013 19:06:01 +0200 Message-ID: <20130403170601.GO2228@phenom.ffwll.local> References: <1364908210-13748-1-git-send-email-ville.syrjala@linux.intel.com> <1364908210-13748-2-git-send-email-ville.syrjala@linux.intel.com> <87hajoncz3.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f52.google.com (mail-ee0-f52.google.com [74.125.83.52]) by gabe.freedesktop.org (Postfix) with ESMTP id E708CE63E0 for ; Wed, 3 Apr 2013 10:03:05 -0700 (PDT) Received: by mail-ee0-f52.google.com with SMTP id d17so741680eek.11 for ; Wed, 03 Apr 2013 10:03:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87hajoncz3.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 03, 2013 at 01:08:16PM +0300, Jani Nikula wrote: > On Tue, 02 Apr 2013, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the > > <=3DGen4/VLV code follow the same pattern as the Gen5+ codepaths. > = > Reviewed-by: Jani Nikula Queued for -next with a pretty massive bikeshed (extended conflict resolutions ftw), thanks for the patch. -Daniel > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_display.c | 123 +++++++++++++++++++--------= -------- > > 1 file changed, 68 insertions(+), 55 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 298bc0c..dfaea15 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4514,6 +4514,71 @@ static void intel_set_pipe_timings(struct intel_= crtc *intel_crtc, > > ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); > > } > > = > > +static void i9xx_set_pipeconf(struct drm_crtc *crtc, > > + const struct drm_display_mode *mode, > > + const struct drm_display_mode *adjusted_mode, > > + bool is_dp) > > +{ > > + struct drm_device *dev =3D crtc->dev; > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > + int pipe =3D intel_crtc->pipe; > > + u32 pipeconf; > > + > > + /* setup pipeconf */ > > + pipeconf =3D I915_READ(PIPECONF(pipe)); > > + > > + if (pipe =3D=3D 0 && INTEL_INFO(dev)->gen < 4) { > > + /* Enable pixel doubling when the dot clock is > 90% of the (display) > > + * core speed. > > + * > > + * XXX: No double-wide on 915GM pipe B. Is that the only reason for = the > > + * pipe =3D=3D 0 check? > > + */ > > + if (mode->clock > > > + dev_priv->display.get_display_clock_speed(dev) * 9 / 10) > > + pipeconf |=3D PIPECONF_DOUBLE_WIDE; > > + else > > + pipeconf &=3D ~PIPECONF_DOUBLE_WIDE; > > + } > > + > > + /* default to 8bpc */ > > + pipeconf &=3D ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); > > + if (is_dp && intel_crtc->config.dither) { > > + pipeconf |=3D PIPECONF_6BPC | > > + PIPECONF_DITHER_EN | > > + PIPECONF_DITHER_TYPE_SP; > > + } > > + > > + if (IS_VALLEYVIEW(dev) && > > + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) && > > + intel_crtc->config.dither) { > > + pipeconf |=3D PIPECONF_6BPC | > > + PIPECONF_ENABLE | > > + I965_PIPECONF_ACTIVE; > > + } > > + > > + if (HAS_PIPE_CXSR(dev)) { > > + if (intel_crtc->lowfreq_avail) { > > + DRM_DEBUG_KMS("enabling CxSR downclocking\n"); > > + pipeconf |=3D PIPECONF_CXSR_DOWNCLOCK; > > + } else { > > + DRM_DEBUG_KMS("disabling CxSR downclocking\n"); > > + pipeconf &=3D ~PIPECONF_CXSR_DOWNCLOCK; > > + } > > + } > > + > > + pipeconf &=3D ~PIPECONF_INTERLACE_MASK; > > + if (!IS_GEN2(dev) && > > + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) > > + pipeconf |=3D PIPECONF_INTERLACE_W_FIELD_INDICATION; > > + else > > + pipeconf |=3D PIPECONF_PROGRESSIVE; > > + > > + I915_WRITE(PIPECONF(pipe), pipeconf); > > + POSTING_READ(PIPECONF(pipe)); > > +} > > + > > static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > > int x, int y, > > struct drm_framebuffer *fb) > > @@ -4528,7 +4593,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *cr= tc, > > int plane =3D intel_crtc->plane; > > int refclk, num_connectors =3D 0; > > intel_clock_t clock, reduced_clock; > > - u32 dspcntr, pipeconf; > > + u32 dspcntr; > > bool ok, has_reduced_clock =3D false, is_sdvo =3D false; > > bool is_lvds =3D false, is_tv =3D false, is_dp =3D false; > > struct intel_encoder *encoder; > > @@ -4605,9 +4670,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *cr= tc, > > has_reduced_clock ? &reduced_clock : NULL, > > num_connectors); > > = > > - /* setup pipeconf */ > > - pipeconf =3D I915_READ(PIPECONF(pipe)); > > - > > /* Set up the display plane register */ > > dspcntr =3D DISPPLANE_GAMMA_ENABLE; > > = > > @@ -4618,58 +4680,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *c= rtc, > > dspcntr |=3D DISPPLANE_SEL_PIPE_B; > > } > > = > > - if (pipe =3D=3D 0 && INTEL_INFO(dev)->gen < 4) { > > - /* Enable pixel doubling when the dot clock is > 90% of the (display) > > - * core speed. > > - * > > - * XXX: No double-wide on 915GM pipe B. Is that the only reason for = the > > - * pipe =3D=3D 0 check? > > - */ > > - if (mode->clock > > > - dev_priv->display.get_display_clock_speed(dev) * 9 / 10) > > - pipeconf |=3D PIPECONF_DOUBLE_WIDE; > > - else > > - pipeconf &=3D ~PIPECONF_DOUBLE_WIDE; > > - } > > - > > - /* default to 8bpc */ > > - pipeconf &=3D ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); > > - if (is_dp) { > > - if (intel_crtc->config.dither) { > > - pipeconf |=3D PIPECONF_6BPC | > > - PIPECONF_DITHER_EN | > > - PIPECONF_DITHER_TYPE_SP; > > - } > > - } > > - > > - if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)= ) { > > - if (intel_crtc->config.dither) { > > - pipeconf |=3D PIPECONF_6BPC | > > - PIPECONF_ENABLE | > > - I965_PIPECONF_ACTIVE; > > - } > > - } > > - > > DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe =3D=3D 0 ? 'A' : 'B'); > > drm_mode_debug_printmodeline(mode); > > = > > - if (HAS_PIPE_CXSR(dev)) { > > - if (intel_crtc->lowfreq_avail) { > > - DRM_DEBUG_KMS("enabling CxSR downclocking\n"); > > - pipeconf |=3D PIPECONF_CXSR_DOWNCLOCK; > > - } else { > > - DRM_DEBUG_KMS("disabling CxSR downclocking\n"); > > - pipeconf &=3D ~PIPECONF_CXSR_DOWNCLOCK; > > - } > > - } > > - > > - pipeconf &=3D ~PIPECONF_INTERLACE_MASK; > > - if (!IS_GEN2(dev) && > > - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) > > - pipeconf |=3D PIPECONF_INTERLACE_W_FIELD_INDICATION; > > - else > > - pipeconf |=3D PIPECONF_PROGRESSIVE; > > - > > intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); > > = > > /* pipesrc and dspsize control the size that is scaled from, > > @@ -4680,8 +4693,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *cr= tc, > > (mode->hdisplay - 1)); > > I915_WRITE(DSPPOS(plane), 0); > > = > > - I915_WRITE(PIPECONF(pipe), pipeconf); > > - POSTING_READ(PIPECONF(pipe)); > > + i9xx_set_pipeconf(crtc, mode, adjusted_mode, is_dp); > > + > > intel_enable_pipe(dev_priv, pipe, false); > > = > > intel_wait_for_vblank(dev, pipe); > > -- = > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch