From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] drm/i915: Don't override PPGTT cacheability on HSW Date: Wed, 3 Apr 2013 13:41:05 -0700 Message-ID: <20130403204104.GA11573@bwidawsk.net> References: <1365012390-6465-1-git-send-email-ben@bwidawsk.net> <515C8048.1080503@whitecape.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.localdomain (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id A1B53E5EDD for ; Wed, 3 Apr 2013 13:41:09 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currently there. > > Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want, > so nothing needs to be changed. Sorry for the confusion. > -Daniel I think the existing code is magic that we don't/shouldn't need. But I also see no reason to change it. -- Ben Widawsky, Intel Open Source Technology Center