From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: revert eDP bpp clamping code changes Date: Thu, 4 Apr 2013 21:01:52 +0200 Message-ID: <20130404190152.GX2228@phenom.ffwll.local> References: <1365088777-5358-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f178.google.com (mail-ea0-f178.google.com [209.85.215.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A4F5E5F09 for ; Thu, 4 Apr 2013 11:58:56 -0700 (PDT) Received: by mail-ea0-f178.google.com with SMTP id o10so1152344eaj.9 for ; Thu, 04 Apr 2013 11:58:55 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 04, 2013 at 03:44:01PM -0300, Paulo Zanoni wrote: > Hi > > 2013/4/4 Daniel Vetter > > > > The behaviour around handling the eDP bpp value from vbt has been > > slightly changed in > > > > commit 3600836585e3fdef0a1410d63fe5ce4015007aac > > Author: Daniel Vetter > > Date: Wed Mar 27 00:44:59 2013 +0100 > > > > drm/i915: convert DP autodither code to new infrastructure > > > > The old behaviour was that we used the plane's bpp (usually 24bpp) for > > computing the dp link bw, but set up the pipe with the bpp value from > > vbt if available. The takes the vbt bpp override into account even for > s/The/This/ ? > > > the dp link bw configuration. > > > > On Paulo's hsw machine this resulted in a slower link clock and a > > black screen - but the mode actually /should/ fit even with the lower > > clock. Until we've cleared up simply stay bug-for-bug compatible with > > the old code. > > > > While at it, also restore a debug message lost in: > > > > commit 4e53c2e010e531b4a014692199e978482d471c7e > > Author: Daniel Vetter > > Date: Wed Mar 27 00:44:58 2013 +0100 > > > > drm/i915: precompute pipe bpp before touching the hw > > > > Cc: Paulo Zanoni > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++---- > > 1 file changed, 14 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index c5cfec3..658d071 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -741,9 +741,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, > > /* Walk through all bpp values. Luckily they're all nicely spaced with 2 > > * bpc in between. */ > > bpp = min_t(int, 8*3, pipe_config->pipe_bpp); > > - if (is_edp(intel_dp) && dev_priv->edp.bpp) > > - bpp = min_t(int, bpp, dev_priv->edp.bpp); > > - > > for (; bpp >= 6*3; bpp -= 2*3) { > > mode_rate = intel_dp_link_required(target_clock, bpp); > > > > @@ -781,7 +778,6 @@ found: > > intel_dp->link_bw = bws[clock]; > > intel_dp->lane_count = lane_count; > > adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); > > - pipe_config->pipe_bpp = bpp; > > pipe_config->pixel_target_clock = target_clock; > > > > DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", > > @@ -796,6 +792,20 @@ found: > > > > intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); > > > > + /* > > + * XXX: We have a strange regression where using the vbt edp bpp value > > + * for the link bw computation results in black screens, the panel only > > + * works when we do the computation at the usual 24bpp (but still > > + * requires us to use 18bpp. Until that's fully debugged, stay > > We're missing a ')' character. > > Reviewed-by: Paulo Zanoni > Tested-by: Paulo Zanoni Fixed up and merged to dinq, thanks for digging into this an reviewing the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch