From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 1/3] drm/i915: fix lost FP_CB_TUNE setting
 for pch plls
Date: Sat, 6 Apr 2013 19:47:26 +0200
Message-ID: <20130406174726.GH2228@phenom.ffwll.local>
References: <1365106834-6201-1-git-send-email-daniel.vetter@ffwll.ch>
	<CA+gsUGRQP9cSwrwk1xZ497p_5wKJpEi=6N7o+h+qzEJ=9RjctA@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com
	[209.85.215.174])
	by gabe.freedesktop.org (Postfix) with ESMTP id 7EB3CE5C05
	for <intel-gfx@lists.freedesktop.org>;
	Sat,  6 Apr 2013 10:44:28 -0700 (PDT)
Received: by mail-ea0-f174.google.com with SMTP id m14so1693475eaj.5
	for <intel-gfx@lists.freedesktop.org>;
	Sat, 06 Apr 2013 10:44:27 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <CA+gsUGRQP9cSwrwk1xZ497p_5wKJpEi=6N7o+h+qzEJ=9RjctA@mail.gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Apr 05, 2013 at 04:52:28PM -0300, Paulo Zanoni wrote:
> Hi
> 
> 2013/4/4 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > commit de13a2e3f88a4da8e85063b6de37096795079e41
> > Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Date:   Thu Sep 20 18:36:05 2012 -0300
> >
> >     drm/i915: extract compute_dpll from ironlake_crtc_mode_set
> >
> > missed the subtle adjustment of the FP1 register. Fix this up by
> > passing a pointer around instead of the value.
> 
> We could also move the whole chunk that sets "factor" and "FP_CB_TUNE"
> back to ironlake_crtc_mode_set or even to a brand new
> ironlake_calculate_fp(intel_crtc, clock, has_reduced_clock,
> reduced_clock, &fp, &fp2). Maybe as a follow-up patch since this
> version is way much easier for -stable.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

All patches merged, thanks for the review. I didn't add a cc: stable to
this one, since no one has reported a regression yet. We can easily
backport if that changes.

I agree with your refactor idea, but until all the clock handling has
settled a bit (due to the massive pipe config reorganisation) I think we
should hold and not waste too much time with beauty-ops ;-)

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch