From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ Date: Tue, 9 Apr 2013 13:54:01 +0200 Message-ID: <20130409115401.GV2228@phenom.ffwll.local> References: <1365497105-13105-1-git-send-email-ville.syrjala@linux.intel.com> <1365497105-13105-2-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f178.google.com (mail-ea0-f178.google.com [209.85.215.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 5120FE5C2B for ; Tue, 9 Apr 2013 04:51:02 -0700 (PDT) Received: by mail-ea0-f178.google.com with SMTP id o10so2845020eaj.23 for ; Tue, 09 Apr 2013 04:51:01 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1365497105-13105-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 09, 2013 at 11:45:05AM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > BSpec contains several scattered notes which state that the maximum > fence stride was increased to 256KB on IVB. > = > Testing on real hardware agrees. > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 7 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i91= 5/i915_gem_tiling.c > index c807eb9..139d17d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, i= nt size, int tiling_mode) > tile_width =3D 512; > = > /* check maximum stride & object size */ > - if (INTEL_INFO(dev)->gen >=3D 4) { > - /* i965 stores the end address of the gtt mapping in the fence > - * reg, so dont bother to check the size */ > + /* i965+ stores the end address of the gtt mapping in the fence > + * reg, so dont bother to check the size */ > + if (INTEL_INFO(dev)->gen >=3D 7) { I've thought that his does not apply to vlv? Or has that now changed? -Daniel > + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) > + return false; > + } else if (INTEL_INFO(dev)->gen >=3D 4) { > if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) > return false; > } else { > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 0e4b7fb..ec4e054 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -424,6 +424,7 @@ > = > #define FENCE_REG_SANDYBRIDGE_0 0x100000 > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 > +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 > = > /* control register for cpu gtt access */ > #define TILECTL 0x101000 > -- = > 1.8.1.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch