From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v2] drm/i915: Reject fence stride=0 on gen4+
Date: Tue, 9 Apr 2013 19:32:50 +0200
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References: <20130409150118.GA2228@phenom.ffwll.local>
	<1365527353-30602-1-git-send-email-ville.syrjala@linux.intel.com>
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On Tue, Apr 09, 2013 at 08:09:13PM +0300, ville.syrjala@linux.intel.com wro=
te:
> From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> Our checks for an invalid fence stride forgot to guard against
> zero stride on gen4+. Fix it.
> =

> v2: Avoid duplicated code (danvet)
> =

> Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_gem_tiling.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> =

> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i91=
5/i915_gem_tiling.c
> index 139d17d..537545b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -238,6 +238,9 @@ i915_tiling_ok(struct drm_device *dev, int stride, in=
t size, int tiling_mode)
>  		}
>  	}
>  =

> +	if (stride < tile_width)
> +		return false;
> +
>  	/* 965+ just needs multiples of tile width */
>  	if (INTEL_INFO(dev)->gen >=3D 4) {
>  		if (stride & (tile_width - 1))
> @@ -246,9 +249,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, in=
t size, int tiling_mode)
>  	}
>  =

>  	/* Pre-965 needs power of two tile widths */
> -	if (stride < tile_width)
> -		return false;
> -
>  	if (stride & (stride - 1))
>  		return false;
>  =

> -- =

> 1.8.1.5
> =


-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch