From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 5/7] drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state Date: Fri, 19 Apr 2013 06:49:35 +0100 Message-ID: <20130419054935.GE23752@strange.amr.corp.intel.com> References: <1366313746-3659-1-git-send-email-przanoni@gmail.com> <1366313746-3659-6-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id CF99EE66AD for ; Thu, 18 Apr 2013 22:49:37 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366313746-3659-6-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 18, 2013 at 04:35:44PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > In the error state function we read the registers without checking if > the power well is on, so after doing this we have to clear the > FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting > it and printing an error message. > > The first version of this patch was checking for the power well state > and then avoiding reading registers that were off, but the reviewers > requested to just read the registers any way and then later clear the > FPGA_DBG_RM_NOCLAIM bit. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien