From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: disable interrupts earlier in the driver unload code Date: Wed, 24 Apr 2013 10:35:16 +0100 Message-ID: <20130424093516.GC11689@cantiga.alporthouse.com> References: <1366795160-2427-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 67EF6E634D for ; Wed, 24 Apr 2013 02:35:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366795160-2427-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Jani Nikula , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 24, 2013 at 11:19:20AM +0200, Daniel Vetter wrote: > Our rps code relies on the interrupts being off to prevent re-arming > of the work items at inopportune moments. > > Also drop the redundant cancel_work for the main rps work, > disable_gt_powersave already takes care of that. > > Finally add a WARN_ON to ensure we obey that piece of ordering > constraint. Long term I want to lock down the setup/teardown code in a > similar way to how we painstakingly check modeset sequence constraints > already. Reminds me, did we every get around to flushing our deferred hw tasks upon suspend? I've a funny feeling that is still missing. -Chris -- Chris Wilson, Intel Open Source Technology Centre