From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/6] drm/i915: IVB FBC
 WaFbcAsynchFlipDisableFbcQueue
Date: Wed, 24 Apr 2013 20:00:06 +0300
Message-ID: <20130424170006.GQ4469@intel.com>
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To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
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On Tue, Apr 23, 2013 at 02:52:17PM -0300, Rodrigo Vivi wrote:
> Display register 42000h bit 22 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
> =

> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  1 file changed, 2 insertions(+)
> =

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel=
_pm.c
> index 86a941a..6315627 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -270,6 +270,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, un=
signed long interval)
>  		   IVB_DPFC_CTL_FENCE_EN |
>  		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
>  =

> +	/* WaFbcAsynchFlipDisableFbcQueue */
> +	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
>  	I915_WRITE(SNB_DPFC_CTL_SA,
>  		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
>  	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> -- =

> 1.8.1.4
> =

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- =

Ville Syrj=E4l=E4
Intel OTC