From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/6] drm/i915: IVB FBC WaFbcDisableDpfcClockGating Date: Wed, 24 Apr 2013 20:15:08 +0300 Message-ID: <20130424171508.GR4469@intel.com> References: <1366739541-4565-1-git-send-email-rodrigo.vivi@gmail.com> <1366739541-4565-4-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 021C7E5F40 for ; Wed, 24 Apr 2013 10:15:11 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366739541-4565-4-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 23, 2013 at 02:52:18PM -0300, Rodrigo Vivi wrote: > Display register 42020h bit 9 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > = > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 6315627..a33490c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -242,6 +242,11 @@ static void ironlake_disable_fbc(struct drm_device *= dev) > dpfc_ctl &=3D ~DPFC_CTL_EN; > I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); > = > + if (IS_IVYBRIDGE(dev)) > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(ILK_DSPCLK_GATE_D, > + ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > + > DRM_DEBUG_KMS("disabled FBC\n"); > } > } > @@ -272,6 +277,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, un= signed long interval) > = > /* WaFbcAsynchFlipDisableFbcQueue */ > I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > + You need to preserve the other bits, mainly ILK_VRHUNIT_CLOCK_GATE_DISABLE. > I915_WRITE(SNB_DPFC_CTL_SA, > SNB_CPU_FENCE_ENABLE | obj->fence_reg); > I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); > -- = > 1.8.1.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC