From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue Date: Wed, 24 Apr 2013 20:38:33 +0300 Message-ID: <20130424173833.GT4469@intel.com> References: <1366739541-4565-1-git-send-email-rodrigo.vivi@gmail.com> <1366739541-4565-6-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 548AAE5CF2 for ; Wed, 24 Apr 2013 10:38:46 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366739541-4565-6-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 23, 2013 at 02:52:20PM -0300, Rodrigo Vivi wrote: > Display register 420B0h bit 22 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > = > Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 2 files changed, 11 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index f64f118..cb2d74c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -864,6 +864,13 @@ > #define IVB_FBC_RT_BASE_ADDR_SHIFT 12 > = > = > +#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 > +#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 > +#define HSW_BYPASS_FBC_QUEUE (1<<22) > +#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ > + _HSW_PIPE_SLICE_CHICKEN_1_A, + \ > + _HSW_PIPE_SLICE_CHICKEN_1_B) > + > /* > * GPIO regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 972a1a3..f81b25f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -280,6 +280,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, u= nsigned long interval) > I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); > /* WaFbcDisableDpfcClockGating */ > I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > + } else { > + /* WaFbcAsynchFlipDisableFbcQueue */ > + I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > + HSW_BYPASS_FBC_QUEUE); > } > = > I915_WRITE(SNB_DPFC_CTL_SA, > -- = > 1.8.1.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC