From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/6] drm/i915: IVB FBC WaFbcDisableDpfcClockGating Date: Fri, 26 Apr 2013 12:07:37 +0300 Message-ID: <20130426090736.GI4469@intel.com> References: <1366910125-7180-1-git-send-email-rodrigo.vivi@gmail.com> <1366910125-7180-3-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EA9BE5DE2 for ; Fri, 26 Apr 2013 02:08:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366910125-7180-3-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 25, 2013 at 02:15:22PM -0300, Rodrigo Vivi wrote: > Display register 42020h bit 9 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > = > v2: RMW to preserve other bits (by Ville) > = > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index e7373a5..fed3610 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -242,6 +242,12 @@ static void ironlake_disable_fbc(struct drm_device *= dev) > dpfc_ctl &=3D ~DPFC_CTL_EN; > I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); > = > + if (IS_IVYBRIDGE(dev)) > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(ILK_DSPCLK_GATE_D, > + I915_READ(ILK_DSPCLK_GATE_D) & > + ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > + > DRM_DEBUG_KMS("disabled FBC\n"); > } > } > @@ -270,6 +276,11 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, u= nsigned long interval) > = > /* WaFbcAsynchFlipDisableFbcQueue */ > I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(ILK_DSPCLK_GATE_D, > + I915_READ(ILK_DSPCLK_GATE_D) & ^ Should be '|' > + ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > + > I915_WRITE(SNB_DPFC_CTL_SA, > SNB_CPU_FENCE_ENABLE | obj->fence_reg); > I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); > -- = > 1.8.1.4 -- = Ville Syrj=E4l=E4 Intel OTC