From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/6] drm/i915: HSW FBC WaFbcDisableDpfcClockGating Date: Fri, 26 Apr 2013 12:10:51 +0300 Message-ID: <20130426091050.GJ4469@intel.com> References: <1366910125-7180-1-git-send-email-rodrigo.vivi@gmail.com> <1366910125-7180-6-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 55F4DE5DE2 for ; Fri, 26 Apr 2013 02:10:58 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366910125-7180-6-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 25, 2013 at 02:15:25PM -0300, Rodrigo Vivi wrote: > Display register 46500h bit 23 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > = > v2: Ville suggested to enable it back when disabling fbc to avoid wasting > power. > = > v3: RMW to preserve other bits (by Ville) > = > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 2 files changed, 13 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 922a7a0..82eaa69 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -871,6 +871,9 @@ > _HSW_PIPE_SLICE_CHICKEN_1_A, + \ > _HSW_PIPE_SLICE_CHICKEN_1_B) > = > +#define HSW_CLKGATE_DISABLE_PART_1 0x46500 > +#define HSW_DPFC_GATING_DISABLE (1<<23) > + > /* > * GPIO regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 9d36158..67b6eab 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *= dev) > I915_READ(ILK_DSPCLK_GATE_D) & > ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); > = > + if(IS_HASWELL(dev)) > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, > + I915_READ(HSW_CLKGATE_DISABLE_PART_1) & > + ~HSW_DPFC_GATING_DISABLE); > + > DRM_DEBUG_KMS("disabled FBC\n"); > } > } > @@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, u= nsigned long interval) > /* WaFbcAsynchFlipDisableFbcQueue */ > I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > HSW_BYPASS_FBC_QUEUE); > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, > + I915_READ(HSW_CLKGATE_DISABLE_PART_1) & ^ '|' again. > + HSW_DPFC_GATING_DISABLE); > } > = > I915_WRITE(SNB_DPFC_CTL_SA, > -- = > 1.8.1.4 -- = Ville Syrj=E4l=E4 Intel OTC