From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 6/7] drm/i915: make SDVO TV-out work for multifunction devices Date: Tue, 30 Apr 2013 13:49:31 +0100 Message-ID: <20130430124635.GA1728@cantiga.alporthouse.com> References: <1367323306-13605-1-git-send-email-daniel.vetter@ffwll.ch> <1367323306-13605-7-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 19BE9E5F1E for ; Tue, 30 Apr 2013 05:49:34 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1367323306-13605-7-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 30, 2013 at 02:01:45PM +0200, Daniel Vetter wrote: > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -223,6 +222,10 @@ struct intel_crtc_config { > /* Controls for the clock computation, to override various stages. */ > bool clock_set; > > + /* SDVO TV has a bunch of special case. To make multifunction encoders > + * work correctly, we need to track this at runtime.*/ > + bool sdvo_tv_clock; > + > /* > * crtc bandwidth limit, don't increase pipe bpp or clock if not really > * required. This is set in the 2nd loop of calling encoder's What is becoming less clear over time is what is derived state internal to the modesetting sequence, and what is the state used to select a mode e.g. to decide if two configs are compatible. -Chris -- Chris Wilson, Intel Open Source Technology Centre