From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 02/12] drm/i915: BUG_ON bad PPGTT offset
Date: Thu, 2 May 2013 13:28:23 -0700
Message-ID: <20130502132823.4c974180@jbarnes-desktop>
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To: Ben Widawsky <ben@bwidawsk.net>
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On Tue, 23 Apr 2013 23:15:30 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> Because PPGTT PDEs within the GTT are calculated in cachelines
> (HW guys consistency ftw) we do a divide which will wreak havoc if this
> is wrong, and I know that from experience).
> 
> If/when we move to multiple PPGTTs this will have to become a WARN, and
> return an error. For now however it should always be considered fatal,
> and only a developer could hit it.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 50df194..0503f09 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -85,6 +85,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
>  	uint32_t pd_entry;
>  	int i;
>  
> +	BUG_ON(ppgtt->pd_offset & 0x3f);
> +
>  	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
>  		ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
>  	for (i = 0; i < ppgtt->num_pd_entries; i++) {

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center