From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 04/12] drm/i915: Extract PDE writes Date: Thu, 2 May 2013 14:27:41 -0700 Message-ID: <20130502142741.06dca54f@jbarnes-desktop> References: <1366784140-2670-1-git-send-email-ben@bwidawsk.net> <1366784140-2670-5-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy12-pub.bluehost.com (oproxy12-pub.bluehost.com [50.87.16.10]) by gabe.freedesktop.org (Postfix) with SMTP id D8F33E643F for ; Thu, 2 May 2013 14:26:58 -0700 (PDT) In-Reply-To: <1366784140-2670-5-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Tue, 23 Apr 2013 23:15:32 -0700 Ben Widawsky wrote: > It also makes some sense IMO to have these two functions separate > irrespective of the number of callers. > > Only the single caller for now, but that will change as we add more > PPGTTs. > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +++++++++++++++------- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 11a50cf..975adaa 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -76,18 +76,13 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, > return pte; > } > > -static int gen6_ppgtt_enable(struct drm_device *dev) > +static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) > { > - drm_i915_private_t *dev_priv = dev->dev_private; > - uint32_t pd_offset; > - struct intel_ring_buffer *ring; > - struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; > + struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; > gen6_gtt_pte_t __iomem *pd_addr; > uint32_t pd_entry; > int i; > > - BUG_ON(ppgtt->pd_offset & 0x3f); > - > pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + > ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); > for (i = 0; i < ppgtt->num_pd_entries; i++) { > @@ -100,6 +95,19 @@ static int gen6_ppgtt_enable(struct drm_device *dev) > writel(pd_entry, pd_addr + i); > } > readl(pd_addr); > +} > + > +static int gen6_ppgtt_enable(struct drm_device *dev) > +{ > + drm_i915_private_t *dev_priv = dev->dev_private; > + uint32_t pd_offset; > + struct intel_ring_buffer *ring; > + struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; > + int i; > + > + BUG_ON(ppgtt->pd_offset & 0x3f); > + > + gen6_write_pdes(ppgtt); > > pd_offset = ppgtt->pd_offset; > pd_offset /= 64; /* in cachelines, */ Yep, looks nicer this way. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center