From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 6/6] drm/i915: fix up adjusted_mode tracking
 for interlaced modes
Date: Mon, 6 May 2013 11:24:42 +0200
Message-ID: <20130506092442.GX5763@phenom.ffwll.local>
References: <20130503091923.GK5763@phenom.ffwll.local>
	<1367574591-1714-1-git-send-email-daniel.vetter@ffwll.ch>
	<1367574591-1714-6-git-send-email-daniel.vetter@ffwll.ch>
	<CAKMK7uHfSVZR3Z1vQ_Vz38JQWFSCmi7k11M_iHU88TnFdqD1Kg@mail.gmail.com>
	<CA+gsUGQYg11eQLcnjsq+9O=dq-z3HEt30thH0Q2RStVOXyFA-w@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-wg0-f47.google.com (mail-wg0-f47.google.com [74.125.82.47])
	by gabe.freedesktop.org (Postfix) with ESMTP id 9341BE5F2E
	for <intel-gfx@lists.freedesktop.org>;
	Mon,  6 May 2013 02:21:36 -0700 (PDT)
Received: by mail-wg0-f47.google.com with SMTP id e11so3222690wgh.2
	for <intel-gfx@lists.freedesktop.org>;
	Mon, 06 May 2013 02:21:35 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <CA+gsUGQYg11eQLcnjsq+9O=dq-z3HEt30thH0Q2RStVOXyFA-w@mail.gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, May 03, 2013 at 11:31:46AM -0300, Paulo Zanoni wrote:
> 2013/5/3 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > On Fri, May 3, 2013 at 11:49 AM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> >> With the hw state readout&check code it's important that the values we
> >> keep around are the canonical ones. Unfortunately when adding the pipe
> >> timings readout support I've missed that the write side adjusts the
> >> timings in the pipe config.
> >>
> >> Fix this up.
> >>
> >> Reported-by: Paulo Zanoni <przanoni@gmail.com>
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> > I better be a good example ;-) So:
> >
> > This fixes a regression introduced in
> >
> > commit 1bd1bd806037af04dd1d7bdd39b2b04090c10d2c
> > Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Date:   Mon Apr 29 21:56:12 2013 +0200
> >
> >     drm/i915: hw state readout support for pipe timings
> >
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> 
> To make it super complete, you could also explicitly mention that this
> fixes a WARN when we use interlaced modes :)
> 
> So now I booted it with the eDP + DP-interlaced I was using yesterday
> and I don't see the error message anymore.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Queued for -next, thanks for the review and testing.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch