From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 02/12] drm/i915: BUG_ON bad PPGTT offset Date: Mon, 6 May 2013 11:48:05 +0200 Message-ID: <20130506094805.GC5763@phenom.ffwll.local> References: <1366784140-2670-1-git-send-email-ben@bwidawsk.net> <1366784140-2670-3-git-send-email-ben@bwidawsk.net> <20130502132823.4c974180@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f48.google.com (mail-wg0-f48.google.com [74.125.82.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 46F1BE5FDA for ; Mon, 6 May 2013 02:44:59 -0700 (PDT) Received: by mail-wg0-f48.google.com with SMTP id f11so3207182wgh.15 for ; Mon, 06 May 2013 02:44:58 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130502132823.4c974180@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: Ben Widawsky , Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Thu, May 02, 2013 at 01:28:23PM -0700, Jesse Barnes wrote: > On Tue, 23 Apr 2013 23:15:30 -0700 > Ben Widawsky wrote: > > > Because PPGTT PDEs within the GTT are calculated in cachelines > > (HW guys consistency ftw) we do a divide which will wreak havoc if this > > is wrong, and I know that from experience). > > > > If/when we move to multiple PPGTTs this will have to become a WARN, and > > return an error. For now however it should always be considered fatal, > > and only a developer could hit it. > > > > Signed-off-by: Ben Widawsky > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 50df194..0503f09 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -85,6 +85,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev) > > uint32_t pd_entry; > > int i; > > > > + BUG_ON(ppgtt->pd_offset & 0x3f); > > + > > pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + > > ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); > > for (i = 0; i < ppgtt->num_pd_entries; i++) { > > Reviewed-by: Jesse Barnes Queued for -next with the same s/BUG/WARN bikeshed, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch