From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/4] drm/i915: go back to switch for VLV mem freq detection v2 Date: Mon, 6 May 2013 17:30:46 +0200 Message-ID: <20130506153046.GF5763@phenom.ffwll.local> References: <1367516890-3469-1-git-send-email-jbarnes@virtuousgeek.org> <1367516890-3469-2-git-send-email-jbarnes@virtuousgeek.org> <20130503175211.GA29311@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 27603E607D for ; Mon, 6 May 2013 08:27:40 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hq12so2678322wib.4 for ; Mon, 06 May 2013 08:27:39 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130503175211.GA29311@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, May 03, 2013 at 10:52:11AM -0700, Ben Widawsky wrote: > On Thu, May 02, 2013 at 10:48:08AM -0700, Jesse Barnes wrote: > > Both the docs and the existing code were wrong. So fix both and use a > > switch statement like we do elsewhere to make things simple & clear. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++- > > 1 file changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 0f4b46e..556b989 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev) > > GEN7_RC_CTL_TO_MODE); > > > > valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val); > > - dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3); > > + switch ((val >> 6) & 3) { > > + case 0: > > + case 1: > > + dev_priv->mem_freq = 800; > > + break; > > + case 2: > > + dev_priv->mem_freq = 1066; > > + break; > > + case 3: > > + dev_priv->mem_freq = 1333; > > + break; > > + } > > DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > > > > DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); > > The code does what the author wants it to, but I don't have the doc that > says this: > Reviewed-by: Ben Widawsky First two patches of this series are merged to dinq, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch